Timing analyses using Xilinx Timing analyzer

Mkanimozhi · Oct 5, 2009

Timing analyses

Hi Experts,
Using Xilinx Timing analyzer shall we do the timing analysis of the combinational design.if it is possible how can we do.

Regards,
Kanimozhi.M

Aser · Oct 8, 2009

Re: Timing analyses

When I want to do the timing analysis of the combinational network in FPGA,
I usually attach the registers to its inputs, outputs.
Then I synthesize, P&R it as usual but with the severe CLOCK constraints,
and see the timing reports.
Xilinx shows a set of critical routes with all the delays, which doesn't satisfy the constraints.

dkk1980 · Oct 9, 2009

Re: Timing analyses

You can apply a PAD to PAD constraint in ISE and see whether it meets.

dkk

sanjayk · Oct 11, 2009

Timing analyses

open Timing analyzer. Open the Timing->Run_analysis and then provide the paths.

Timing analyses using Xilinx Timing analyzer

Mkanimozhi

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Aser

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dkk1980

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sanjayk

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Timing analyses using Xilinx Timing analyzer

Mkanimozhi

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Aser

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dkk1980

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sanjayk

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