latch time borrowing
anjali said:
Time borrowing means one latch takes the (a portion of ) clock period from its adjuscent latches by inserting buffers in clock network in proper position.
yes. if you are interesting in this you can read this book more detail.
something about this :
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Slack passing is possible with level-sensitive latches or cycle stealing, by
careful scheduling of the arrival of the clock edges at different registers.
Multi-phase clocking will not be a viable solution in the deep submicron,
because of signal integrity issues and the increasing difficulty of distributing
several clocks across the chip [36].
If the latch inputs arrive within the window while the latches are
transparent, the setup time and clock skew have far less impact on the clock
period. Some high speed pulsed flip-flops have about zero setup time [30],
but they are not transparent, so the impact of the clock skew is not reduced.
As ASICs have large clock skew, latches have substantial benefits for
reducing the clock period.
Also, level-sensitive latches reduce the impact of inaccuracy of wire load
models and process variation. The clock period is not limited by the delay of
the slowest pipeline stage, because of slack passing. Adjusting the clock
skew after layout and extraction of parasitic capacitances can compensate for
wire load model inaccuracies. However, changing the clock trees requires
additional layout iterations.
Clock-related timing issues are tutorially reviewd in Chapter 3
(Chinnery). Chapter 7 (Tensilica – latches) describes a prototype tool that
automatically converts a gate net list with flip-flops to use latches –
experimental results of 10% to 20% speed improvement are reported for a
commercial synthesizable ASIC in a high-performance standard cell ASIC
flow.
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this attach is about the timing theory of latch-base design. and it is good for reading