hannes_knp
Newbie level 1
Hi,
We are using LM3S cortex M3 microcontrollers. We had found a failure mode 2 months ago, without finding any explanation for it (loss of JTAG access, controller does not start up after power up sequence). One week ago, we were informationed that silicon revision C1 and C3 of the tempest class has a small risk of flash corruption or device failure on power up. Now, TI provided us with a workaround, but we have to bear all risks of using this controller.
My Question:
Has someone the same problem and - if yes - how do you estimate/rate the remaining risk?
Thanks for everyone's input.
We are using LM3S cortex M3 microcontrollers. We had found a failure mode 2 months ago, without finding any explanation for it (loss of JTAG access, controller does not start up after power up sequence). One week ago, we were informationed that silicon revision C1 and C3 of the tempest class has a small risk of flash corruption or device failure on power up. Now, TI provided us with a workaround, but we have to bear all risks of using this controller.
My Question:
Has someone the same problem and - if yes - how do you estimate/rate the remaining risk?
Thanks for everyone's input.