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Thyristor - Reverse Diodes and Reverse Blocking

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Jul 22, 2014
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I'm looking to upgrade an existing product that is essentially based around charging one or more caps to HV (multi kV), and discharging (through a thyristor) into a low impedance RL load (typically impedance around 1 ohm). The discharge pulse is very high current (as you can imagine) and lasts a few 100us.

In practice the Thyristor is actually several devices in parallel and series to handle the voltage, current, dI/dt etc. Series inductors, parallel R and RC etc are used to force the necessary sharing. I haven't shown all these to simplify the diagram. Gate drives (again not shown) are isolated and coincident. - All works fine (long proven record).

Now I want to upgrade the solution to allow the option of (optionally) discharging multiple capacitors into the same load using essentially repeats of the capacitor and Thyristor setup shown.
I.E. the Thyristor cathodes (bottom row) will be connected together but not all banks will necessarily fire at the same time (or at all). Capacitors in the banks that are unfired may or may not be charged. This leads to two questions.

1. The above will require the reverse diodes will need to be omitted to allow reverse voltage to develop (if necessary) across the unfired banks. Can anyone think of a problem removing those (not sure what their use is).

2. Is there a fundamental issue with a high speed change in voltage across the unfired banks I.e. either from 5kV to 0kV developed across the unfired Thyristors (cap charged) or 0kV to -5kV (cap uncharged). I would have thought any dV/dT issues wouldn't be an issue as the voltage is reversing but not sure what else could go wrong.


  • Thyristor.PNG
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A fair guess for 1) is that the diodes are like ESD or H-bridge diodes, etc. - to dump spikes back into the power supply and protect other components, like relay flyback diode. Maybe.

2) Can't help, sorry. Surely datasheet and/or thyristor app notes, etc. from manufacturers and tutorials about how they work dedicate plenty of space to that topic?
Your SCRs should have a VRRM (repetitive peak reverse voltage) rating, and a VRSM non repetitive peak reverse voltage rating.
Provided there is some suitable resistance/capacitance across each device to ensure both dc and transient voltage sharing, which you probably already have, I doubt there will be issues.

The biggest worry might be any ringing or transients produced that could add to the anticipated voltage stress. Any pulse forming network needs to be critically damped, but you already know that.
The whole physical layout needs some very careful planning...

One final thought.
Discharging this monster at widely different power levels will change the impedances, and that could effect damping.
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for SCR's in parallel you need small air cored chokes in series with each to obtain a measure of transient current sharing at turn on
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