Throughput calculation on design in XIlinx

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ramdin2006

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How to calculate throughput, latency from a simulation of verilog design?
 

Latency is the number of clocks between inputting data and getting an output.
Throughput is calculated by inputing a known amount of data in a specific time frame, and multipying the value in bits/s. Depending on the design, you can usually calculate a theoretical throughput from the architecture, but you may have to measure it on real hardware for real life results.
 


If this is the simulation result, what would be the latency and throughput of the design? Could you explain me. Thanks.
 

Without knowing the design, or seeing the code, I have no way of working that out from a very limit waveform.
 

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