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But PMOS can tend to have a higher mV/decade subthreshold
slope than NMOS, so you might have to target a higher
VT in order to ensure that you are on the leakage floor
and not seeing subthreshold leakage in all of your logic.
But it's entirely the fab's discretion, not something set in
With length, you have short channel effects, DIBL and the
like from increased net-field-sum etc.
If you are taking "VT" as a fixed current and not ratioed
against the W/L, you will arrive at a strongly geometry-varying
(as the current is strongly geometry-varying) result.
Delta-W effects I would not expect to mean much, but at
near minimum drawn widths they may add significantly
to the conduction, the "bird's beak" LOCOS taper region
can be a different actor than the explicit channel in many
ways, most of them not good.