The output logic state can take on 2 "valid" states, and 1 state where the output
is unaffected by any device inputs :
A valid state where the output meets the Vol and Voh specs in datasheet for that logic
family. Different logic families can have different valid levels, TTL, COS, ECL, LVDS........
Thats when the output totem pole output transistors, the drive to a low and drive to a high,
are both off, Q3 and Q4 in this example. So pin V is only affected by leakage and thats
unpredictable. This is tristate logic and allows one to connect multiple devices to the same
buss, share the buss, one at a time when enabled to control the buss.
CMOS looks like :
Tri-state here is when both PMOS and NMOS transistors off.
Some designs will use R pullup or pulldown R's so that when nothing
is driving the buss the R's will force a logic 0 or 1 as a default on the
buss. Thats desired so that any inputs, in case of CMOS logic, do not
float and draw power in their input buffers. But any device that takes
control of buss can drive the R's to desired state.
Regards, Dana.