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Three questions about the vhdl, please help

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vhdl help

hello,

can u please tell me how to use a package in the vhdl ?
and how to write function that return more than one output?
and if i want to define a variable but in time domain how can i do it?

thanks in advance
 

vhdl help

u can make a file with any name for example pkg.vhd and call it in another file by writing Use work.pkg.all.

I did not get this.""if i want to define a variable but in time domain how can i do it? ""
 

Re: vhdl help

vikas_lakhanpal27 said:
u can make a file with any name for example pkg.vhd and call it in another file by writing Use work.pkg.all.

I did not get this.""if i want to define a variable but in time domain how can i do it? ""

for example i want to define a variable called delta=wo/B.W and i want to use these delta after that in time domain ex.s<=s+1 after delta , how can i define it as a time domain variable?
 

Re: vhdl help

1, eg:
library ieee;
use ieee.std_logic_1164.all
In this example, std_logic_1164 is a package.

2, In functions, since it requires a return type, I don't know if there is some other ways to handle multi output problem. But what I can think of is to use a record type as output type. You can of course define as many outputs in the record type as you like.

3, I don't think it can be done since according to my memory, all the "after" statement will be removed during the synthesis.
 

Re: vhdl help

Alexander Yin said:
1, eg:
library ieee;
use ieee.std_logic_1164.all
In this example, std_logic_1164 is a package.

2, In functions, since it requires a return type, I don't know if there is some other ways to handle multi output problem. But what I can think of is to use a record type as output type. You can of course define as many outputs in the record type as you like.

3, I don't think it can be done since according to my memory, all the "after" statement will be removed during the synthesis.


for 3- it's for simulation only i don't want to synthesis it
 

Re: vhdl help

can u please tell me how to use a package in the vhdl ?
for this
do the library declaration and then creat package
by using this "use work.packagename.all ;
use in your design

and how to write function that return more than one output?
function return only one value but you need two return go for procdure
in procedure you can take more than on output

and if i want to define a variable but in time domain how can i do it?
ex : variable var_name : time := initial value(5 ns ) ;
 

Re: vhdl help

you should just use the units of time: ns, us, ms....etc

for instance:
a <=b after c ns;

a will take the value of b after c ns

or you can define your own units of time, by having another type for them!
but i don't think you'll need this, not with time units at least
 

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