ebuddy
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I am looking at a chip spec. It uses a single wire to do both power supply and digital serial input/output. This pin, plus a ground pin, are all the pins this chip has.
In normal use, the power pin is connected to VDD thru a pull-up resistor. The digital signal can be transmitted on this same wire by pulling it low momentarily. When the power line is pulled low, the chip internal supply is provided with the on-chip parasitic capacitor holding the charges.
The interesting thing is, the spec claims the parasitic capacitor is 1000pf. How did they do that? The die size is roughly 2mm x 2mm. Even if the chip is filled with by-pass caps, and uses all the metals to do the cap, it is still hard to have such big cap. Any possible tricks?
In normal use, the power pin is connected to VDD thru a pull-up resistor. The digital signal can be transmitted on this same wire by pulling it low momentarily. When the power line is pulled low, the chip internal supply is provided with the on-chip parasitic capacitor holding the charges.
The interesting thing is, the spec claims the parasitic capacitor is 1000pf. How did they do that? The die size is roughly 2mm x 2mm. Even if the chip is filled with by-pass caps, and uses all the metals to do the cap, it is still hard to have such big cap. Any possible tricks?