The "unknown status" can cause a "lock status

[machael]

Hello everyone,
I am now testing an ASIC design. I found that the chip will randomly enter a "lock status" after power is on---- no expected pulse output. I have found that it was because of a bug of power-on reset logic, the reset wire is always high when power is on, so some registers did not be set the expected value and in fact in a "unknown status" (x).

I have tried to trace the source of the "lock logic" when "unknow status" is generated, so I write a testbench and in initial block I set some random value to the registers which should be resetted when power is on. However, I didn't found the system could enter a lock-status.

So I am confused, I don't know if there exist a "status combination" which could lead to a lock and I just did not found it fortunately (I don't think that is possible because my logic is not complex), or my concepts about "unknown status" is wrong. In my opinion, the "unknown status" is a unknown but certain logic status, it could be "1" or "0" randomly. Is my opinion wrong?

Please think about my question and give me some advise. I will appreciate that very very much!

Machael.

 

[haosg]

Re: The "unknown status" can cause a "lock st

your thought is right, but randon number could not cover all combinational.
In design stage, you should put big care on FSM to make it can return default state(for example, IDLE) form any other state, thus, though reset did not work, you can also set some command to make FSM normal work.
If you omit the check, the lock or un-controllabel FSM occured.
Detaild check FSM, to find out state that could not return to default state.
It may be helpful

 

[kctang]

Re: The "unknown status" can cause a "lock st

Another point is in real chip, power-on-reset has to be taken care. It is always a good practice that external master reset is present. If the on-chip POR is not working , you can connect your external master reset with some RC or power on supervisory chips.

 

[machael]

kctang,
My chip has an power on supervisor function module inside. So it could not be the problem of "power on slowly". But I thank for your kindly reminding. ^_^
machael

Added after 2 hours 6 minutes:

haosg,
Thanks for your help. So it seems that I have to recheck it more carefully.... Do you know is there any software who has this function that it can analyse the FSM status of your design thoroughly and report whether any lock or unexpect status exists?
machael