The timing mode of the core generated by Coregen of Xilinx

[Joyee]

xilinx coregen timing model

As we know, if we instantiate the core generated by Core generator of Xilinx, the timing performance will improve dramatically. However, as our design including the hdl codes except the core of Coregen should be processed by synthesis tools, Synplify, and the tools often depend on the timing-driven method to optimize the design, how could we offer a timing mode of the generated core to the tools? However, firstly, where we can get such a timing mode for the generated core? It's obversily that lack of timing mode for the core will compromise the performance of synthesis tools.

 

[buzkiller]

Search Synplify Pro help for topic "Black-Box Timing Model".
For timing data itself look at the datasheet of the core.

regards,
Buzkiller.