I never liked the stb tool, maybe you should try an
old school analysis (ac, use vcvs to pick off input
difference voltage, use Calculator to plot AV and
phase). That way you will see whether it's the op
amp or the analysis that's messed up.
I never liked the stb tool, maybe you should try an
old school analysis (ac, use vcvs to pick off input
difference voltage, use Calculator to plot AV and
phase). That way you will see whether it's the op
amp or the analysis that's messed up.
To me, the most reliable stab. analysis is simply to plot the small-signal loop gain (magnitude and phase) vs. frequency and check the stability margin (based on the stability criterion).
Might suggest putting trivial resistors (like 10mOhm)
in series with symbol terminals, between it and the
"outside world". I have found some behaviorals do not
act right regarding terminal currents, but the analogLib
resistor does not lie.
But give a classical, ac simulation a try, and plot gain
& phase in the usual way. Then you will be able to say
- the cell works and stb does not
or
- the cell does not work (as parameterized) and stb is
telling you so
Since the DC offset is roughly what you told it, I'd be
inclined to think the cell is "good" (for DC at least).
Might suggest putting trivial resistors (like 10mOhm)
in series with symbol terminals, between it and the
"outside world". I have found some behaviorals do not
act right regarding terminal currents, but the analogLib
resistor does not lie.
I try to do your suggestion, but they are not work.
So I change the cadence environment form IC616 to IC5141,
the simulation is work (PM = 14, Gain = 60dB)
I think the problem is my cadence environment issue.
So I closed this topic.