The SLew rate in the pipeline ADC and SDM modulator

[mitgrace]

Dear All :

Does anyone know how to sepcific the S.R of op in the pipeline SDC or SDM.
if the 10bits 40MHz ADC , how to define the every satge opamp specific ? Thanks

 

[safwatonline]

it affects the settling error of the opamp (along with the DC gain and the linear settling), you should spec it to be a small part of ur total error budget ,note each stage error contributes according to its order in number of stages (i.e. the first has majour contribution then second then ...)

 

[mitgrace]

Dear Sir :
I have know how to define the opamp DC gain , and Fu for stage, But I still understand about the slew rate. I read some paper , The slew rate is large signal depend on the CL and CLK rate, But actually I still under, if I have ADC specific , example 10bits ADC, Vinswing is 1v per line, How to define the slew rate. Thanks