Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

the ration of channel width of PMOS and NMOS???

Not open for further replies.


Junior Member level 3
Jul 7, 2007
Reaction score
Trophy points
Activity points
To design a CMOS invertor with balance rise and fall time, please define the ration of channel width of PMOS and NMOS and explain?

if u want a balanced inverter with a normal skew 2/1 shud be mobility ratios are between 2-3 ...u can use PN ratios for average delay as arnd 1.5....u can hold this ratio and decide the width of ur pmos and nmos based on output fanout/load...

Added after 30 seconds:

And...u can pick any logical effort info...and chk the same....

It varies from technology to technology.

You need to simulate and get the results accurately. However the results will largely depend on the model cards that you are using, that is what decides the mobility ratio and hence the width ratio.

Strictly it would be wrong to quote any numbers here but you can take wp~2.5wn - not exact, only a rough idea).

PMOS:NMOS --> 2:1

Yes indeed,
electron mobility is 2 times the holes mobility so PMOS width must be 2 times of NMOS width.

Is not the mobility ratio 3:1?.

You can do a hspice simulation with varying ratios and analyse the results on awaves. That should give you a rough idea of the ratio that you would need.


To be accurate, you'd better use spice to simulate the inverter with associated technology model. Roughly, the ratio is in 2-2.5. The mobility is not the only factor you need to consider , there are also some other factors: parasitic capacitance is one of them, which has different weight for different technology

Not open for further replies.

Part and Inventory Search

Welcome to