Delays in digital gate
In TTL logic device, which use bipolar transistor T(PHL) not equal to T(PLH).
because of switching charachteristic of BP transistror.
in BP transistor we have 4 timing regions.
turn on delay time, rise time, storage time, and fall time.
storage time compared to other timing is very long.
and this produce extra time needed to turn off transistor.
for over come to this problem shottky TTL borned.
I think in all other logic device similar phenomena cause this inequality.
Regards,
Davood.