Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

the parasitic cap value of PAD for 0.5um cmos process

Status
Not open for further replies.

h.martin

Member level 1
Joined
Jan 13, 2006
Messages
32
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Location
xi'an china
Activity points
1,478
cmos parasitic cap

can anybady tell me the parasitic value of 90*90um^2 PAD for 0.5um cmos process? thanks
 

Hi
as I know there are various types of pad.
pads have some circuits such as buffers and ECD protection circuits.
regards
 

It depends on PAD strucure and process. Typically you can use 5pF and 10pF for the worse case.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top