the output is shifted by one clock VHDL

[Osama7assan]

in simulation a code for QAM mapping used in OFDM .. the code is working great but i have a problem

the output is shifted by one clock

the output that should appear in clk 1 with input11 appears in clk 2 with input 2 and so on
the code is
this is not clearly my code


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;


entity qam is
port (
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(1 downto 0);
Iout : out std_logic_vector(11 downto 0);
Qout : out std_logic_vector(11 downto 0));
end qam;

architecture qam of qam is

begin

process (clk, rst)
constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
begin
if rst = '1' then
Iout <= (others => '0');
Qout <= (others => '0');
elsif clk'event and clk = '1' then

case input is
when "00" =>
Iout <= mais1;
Qout <= mais1;
when "01" =>
Iout <= menos1;
Qout <= mais1;
when "10" =>
Iout <= mais1;
Qout <= menos1;
when others =>
Iout <= menos1;
Qout <= menos1;
end case;
end if;
end process;

end qam;

 

[FvM]

The input is transferred to ouput on the rising edge of clk. It is not shifted.
The problem is either in the testbench or a lack of understanding synchronous logic.

Depending on the design purpose, you might want to code a pure combinational process without a clock.

 

[Osama7assan]

FvM thanks for your quick reply

i knew that when the clk rising takes the input for the next clk
tried to make the condition .. if clk = '1' then .. without clk'event .. that was useful on previous programs .. but in this program no way

when doing the condition without clock the out put appears is the middle of the clock .. i think at falling edge !! not useful again .
when i cancel the clk before it rising or cancel the input before the clk catch it the output was as i need "was right" .. but this solution is not practical and can't use it .


can u help me ?

 

[FvM]

when doing the condition without clock the out put appears is the middle of the clock .. i think at falling edge !! not useful again

Surely not at the falling clock edge, but delayed by a certain amount of time.

Without knowing the design purpose, particularly the target of Iout and Qout, no suggestion is possible.

By nature of synchronous logic, signals are registered on a clock edge, processed in a combinatorial block, registered on the next clock edge and so on. The delay doesn#t affect the processing speed as long as the data is streaming through the design and all data pathes are delayed by the same number of clock cycles. It might be necessary to add extra register levels at some places in the design to fit the delays.

 

[Osama7assan]

FvM thanks for your help

the solution is
1- doing the condition without clock .. replace it with { if rst = '0' then}
2- putting input between the process quotation marks.


process (clk, rst,input)
constant mais1 : std_logic_vector(11 downto 0) := "001100000000";
constant menos1 : std_logic_vector(11 downto 0) := "110100000000";
begin
if rst = '1' then
Iout <= (others => '0');
Qout <= (others => '0');
elsif rst = '0' then

 

[FvM]

Yes, that's th ementioned pure combinatorial process.

instead of "elsif rst = '0' then", you can write "else" in this case, but it doesn't change anything to the generated logic.