the MOSFET device's problem of the DC MOTOR

[Small_hill]

Dear friends:
I have made a DC MOTOR's device using H bridge MOSFET ciruit.I used two pieces of LM5109 which had driven H bridge MOSFET Ciruit.(LM5109 is half-bridge MOSFET's chip)I could still get PWM to drive H bridge working.
NOW,I find the working DC MOTOR can make produce unnecessary wave in MOTOR's POWER.why? I should how to solve it?


Please I would appreciate any help!!

Small hill!

 

[ArNvC]

The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout, I think you should consider the following:
Firstly, a capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external
MOSFET preferably a low valued capacitor.

To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).

And, in order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.

 

[Small_hill]

Dear arumava7:
I want to know how to avoid large negative transients on the switch node pin,and how to minimize the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET. Maybe you can show some relevance theories to me.
I would appreciate any help!!

small hill!

 

[ArNvC]

For the Parasitic Inductances in Mosfets will depend on how well you organise the PCB or the veroboard you are using. Generally speaking, to minimise the parasitic inductance value, the length through which the current passes must be minimised and the cross sectional area through which current flows maximised.

Both the problems can be minimised by using a Snubber. The snubber reduces the voltage transient and damps the subsequent ringing with the parasitic capacitance that occurs when the switch opens.

 

[Small_hill]

For the Parasitic Inductances in Mosfets will depend on how well you organise the PCB or the veroboard you are using. Generally speaking, to minimise the parasitic inductance value, the length through which the current passes must be minimised and the cross sectional area through which current flows maximised.

Both the problems can be minimised by using a Snubber. The snubber reduces the voltage transient and damps the subsequent ringing with the parasitic capacitance that occurs when the switch opens.

thanks so much for replies!