Considerer two flip flops (FF1 and FF2) that have logic stuff between them (AND, OR etc..)
You need to be sure that you garantee the:
Short path condition
ζQm1 + ζPm > ζH2 + ζC
Where Q index refers to the FF 1 delay, m to the minimum, ζPm refers to the delay caused by the logic stuff between the two flip flops, ζH is the hold time of FF2 , ζC is the clock skew.
For the long path condition you have:
ζQM1 + ζPM + ζS < ζTw - ζC
where ζS is the setup time of FF1 and ζTw is the clock pulse width