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The layout structure depends on the architecture you have followed. If it is an segmented architecture, where you have a unary plan, you could go for matrix type layout for the LSB part with randomizing the cells in the matrix (for taking care temp. gradient) and concept of local and global bias. Two documants would be helpful in this regard. These are listed below. If you need these, can write me...
1.A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm/sup 2/ segmented current steering CMOS DAC
Haider, S.; Banerjee, S.; Ghosh, A.; Ravi sankar Prasad; Chatterjee, A.; Kumar Dey, S.;
VLSI Design, 2005. 18th International Conference on
3-7 Jan. 2005 Page(s):319 - 322
Digital Object Identifier 10.1109/ICVD.2005.6
2.A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter
van den Bosch, A.; Borremans, M.A.F.; Steyaert, M.S.J.; Sansen, W.;
Solid-State Circuits, IEEE Journal of
Volume 36, Issue 3, March 2001 Page(s):315 - 324
Digital Object Identifier 10.1109/4.910469
If u hav done current steering DAC with segmented architecture then u should match all the transistors in the layout & floorplan ur layout to seperate analog & digital parts,
surround each mached pair of NMOS or PMOS with double gaurdrings,separate analog & digital parts with a gaurdring