Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE
you are showing the results from the start of time at t=0. most practical designs will either make inputs as valid some time after a reset, or will ignore some number of samples after reset.
It isn't clear to me if this is just a testbench issue (eg, cores held in reset for 100 ns), an issue at startup (internal resets that take 100 ns), a lack of understanding of bandwidth vs latency (multiple-cycles to get a result), or an actual delay (modeling a combinatorial delay for a core that is actually slow).
My guess is a combination of a reset that lasts ~100ns and addition of maybe 7-8 cycles of latency in addition to a clock that starts low. (the latter is only there to explain 115ns vs 114ns or 116ns)