The differences within u1, u2, u3 and u4 in port mapping

i do not know the differences within u1, u2, u3 and u4.
who can help me?
thank you!

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY nd2 IS
PORT ( a, b: IN STD_LOGIC;
c: OUT STD_LOGIC );
END nd2;

ARCHITECTURE nd2behv OF nd2 IS
BEGIN
c <= a NAND b;
END nd2behv ;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ord41 IS
PORT ( a1, b1, c1, d1 : IN STD_LOGIC;
z1 : OUT STD_LOGIC );
END ord41;

ARCHITECTURE ord41behv OF ord41 IS
COMPONENT nd2
PORT ( a, b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END COMPONENT;

BEGIN
u1 : nd2 PORT MAP (a=>c1, b=>d1, c =>z1); --right
u2 : nd2 PORT MAP (c1=>a, d1=>b, z1 =>c); --error
u3 : nd2 PORT MAP (c1<=a, d1<=b, z1<=c); --error
u4 : nd2 PORT MAP (a<=c1, b<=d1, c<=z1); --error

END ARCHITECTURE ord41behv;

[help]+port map

on all port maps, you follow the following rules:

component port => signal/top level port.

so c1 <= a is wrong, it should be:

uX : nd2 port map (
a => c1,
b => c2,
c => c3
);

This is the only correct format.