yassin2705
Junior Member level 1
Hi,
I am about to start learning verilog language to use it in the modeling of analog blocks such as VCO, Filters & so on. I don't know the difference between verilog, veriloga & verilog-AMS. Also what are the differences between verilog or VHDL?
Thanks!
I am about to start learning verilog language to use it in the modeling of analog blocks such as VCO, Filters & so on. I don't know the difference between verilog, veriloga & verilog-AMS. Also what are the differences between verilog or VHDL?
Thanks!