Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

the difference between ungroup and set_flatten commands

Status
Not open for further replies.

owen_li

Full Member level 3
Joined
Jul 22, 2007
Messages
150
Helped
17
Reputation
34
Reaction score
15
Trophy points
1,298
Activity points
2,301
set_flatten

What is the difference between ungroup and set_flatten commands in Design Compiler? It seems that they are both used to flat the design. Help me!
 

design compiler ungroup

the ungroup command removes the hierarchy in the design (netlist) and make it flat..
you can use set_flatten command (options are true and false) to enable and disable this behavior during logic optimization (during compile)...
By default it is set to be false...
 

ungrouping a module design compiler

Ungrouping will remove the levels of hierarchy in a design , where as flatening (Set flatten) is optimization technique for reducing the logic levels and improving the speed of the design.

Flatening works by converting the combo logic into two level SOP(sum-of-product) form and removing intermediate terms. where as by ungrouping the design , by which removing the hierarchy and combining two logic blocks,It will produce more optimization solution.

Flatening is controlled by User. Default its off. Depends on the arithemetic logic used in your design, you can enable set flatten command. Flatening is expensive solution.

How set_flatten Worsk in DC :
Product = X * W;
X = Y+Z;
when you set , set_flatten true in DC , the optimization will be ,
product = (Y+Z) * W => Y*W + Z * W;




Flattening optimization technique used only in the regular compile , not in the incremental compile.
 

difference between ungroup and flatten in dc

set_flatten ---> u shud be knwing compilation process....
in logic optimization... there r two types of optimization
1) structural(default)
2) flattening

by default, structural optimization takes place..... to enable flattening ---(plz note tht.. flattening doesnt mean removing hierarchy... in some circumstance v mean tht..)

ungroup is to remove hierarchy !!
regards
Shiv
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top