The difference between Slice Logic Utilization and Slice Logic Distribution in Xilinx

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vivek_p

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What is the difference between Slice Logic Utilization and Slice Logic Distribution in Xilinx ISE............Can anyone please explain about slices and LUTs
 

Re: Xilinx

you know the floorplan editor might help you learn about slices

and the LUT's are Look up Tables
 

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