Re: diff b/w RTL and HDL
An HDL is simply hardware descriptive language such as VHDL , Verilog etc. Now these languages supports constructs which are synthesizable as well as non synthesizable.
Any HDL code , written in any model(behavirola, structural etc.) becomes an RTL in official terms only when it is is synthesizable. If an HDL code contains constructs such as (wait) which are not synthesizable then that code cannot be stated as RTL as we cannot generate hardware from that code.
I hope now it is clear.