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RTL is a style of coding synthesizable VHDL or Verilog. In other words, it's how you describe your circuit in VHDL/Verilog so as you can synthesize it later. This means that the style you use for coding VHDL/Verilog testbenches may not be written in RTL as it's not intended to be synthesized.
FPGA (a competitor of ASIC) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
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