The DFM issues in ASIC design

[ameed]

hi all,


For a small Full custom design, a designer who is fully aware of the DFM issues can do his bit

to increase the yield. But finally in a big chip design the designer has to be dependent on the

EDA tools to do this.

Most of the EDA companies have come out with tools which take care of these DFM issues. But

the universal success of such tools is still unknown!!
can anyone suggest:?:

 

[analog_prodigy]

asic design

I think, synopsys tools are good for digital and cadence tools are good for analog chips. Monte Carlo analysis helps us in determining the yeild.