Hi,
Would you help to take a look at the attached datasheet from Honeywell corporation?In page 463, the specifications of pulse width distortion is defined as 5% in typ and 10%in max.What does it mean?
Is it mean the dutycyle distortion?I.e., the duty cycles is 45% in typ and 40% in max?
Hi IanP,
May I ask you a question on the PWD again? The question puzzles me for some time.
I always found the datasheet of optical receiver gives the specifications on the PWD.It is defined as the pulse width of "1"-pulse width of "0",then divided by two. The product I used in 155Mbps always gives the 25ps in typ and 300ps in max, for example.
The question is I found the crossing poin of the eye-diagram for our chip is shifted up/down seriously,it sometimes even reachs to the top or bottom of the eye-diagram.But at this time, the PWD is still fall into the spec, i.e., the max PWD is still less than the 300ps in MAX as speced It is because of the rise/fall time very sharp. But the crossing point of the eye-diagram has shifted from midpoint very seriously. I want to know, is it will affect the application?Or will it affect the function of the following stage?
I am designing a optical receiver. I have completed the design. The simulation shows that the PWD is entering the spec for all the PVT corners,but in some cases,the crossing points shifted seriously. So, I am not sure if my design can be freezed.