The definition of synthesis process

[Manish Sharma]

synthesis ?

hi
if any one explain the synthesis and the harware implementation what is the synthesis? how we can do it with our complied code or after simulation in model sim ......

 

[masai_mara]

Re: synthesis ?

Synthesis is the process of converting the algorithm in your RTL code into a set of hardware realisable components like AND, OR gates, etc. In case of FPGA systhesis these components are called primitives supplied along with FPGA tools and in case of asic systhesis these components are called asic library components developed by a particular asic library developer. So in effect systhesis tool uses these libraries or primitives and your rtl code and turn it into a standard gate level netlist which is in turn fed to a FPGA PAR(place and route) tool or asic par tool to do the actual physical systhesis.

 

[eexuke]

Re: synthesis ?

Synthesis is trying to convert your RTL netlist into gate-level netlist which consists of AND/OR/NOR....... gates from the library you specified during synthesis. After synthesis,you should do formal verification and a preliminary timing analysis,then you can do trial layout to assess your design. Synthesis->analysis->P&R->re-synthesis may have several iterations like this.

 

[zhangpengyu]

synthesis ?

Synthesis is to convert RTL code to gate-level netlist.
It will optimize your code , according your requset of area,time,power.

 

[heartfree]

synthesis ?

Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function.
It's the bridge between RTL & Gate-level.
Synthesis = Translation + logic optimization + Mapping(gate-level optimization).

 

[Manish Sharma]

Re: synthesis ?

hi
i am using the model sim for the simulation and fpga so what should be the stepwise processes to go thru the synthesis ,if i ve got the simulated code ....... that is the question ? how do we do that in fpga.

 

[jobnom99]

Re: synthesis ?

if you have simulated RTL code , and you decide to FPGA target devices.

in normal case , there is 2 ways to synthesis.

1. FPGA SW provided FPGA Vendor

for example , you can use max2plus or quatus of altera , if you use Altera.
you cans use Xilinx ISE ,if you use Xilinx etc.
in that program , you can do synthesis and FPGA fitting(targetting).
for SW , pls contact altera and xilinx web sites.

2. commercial synthesis tool

in FPGA field , almost people use synplicity synplify_pro for synthesis SW.
synplify_pro can support various FPGA vendor and devices.


I think synplify_pro is good solution.

 

[atmaca]

Re: synthesis ?

implementation is the realization of any synthesis as an ic
thanks

 

[tom123]

Re: synthesis ?

SYNTHESIS is translation(translate RTL to general logic expression), optimization

(reduce logic), map(map reduced logic to target library gates).

hi
if any one explain the synthesis and the harware implementation what is the synthesis? how we can do it with our complied code or after simulation in model sim ......

 

[no_mad]

Re: synthesis ?

After you have simulated the code using Modelsim, i would like to suggest you use Leonardo Spectrum to synthesis your design.

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Added after 17 seconds:

After you have simulated the code using Modelsim, i would like to suggest you use Leonardo Spectrum to synthesis your design.