Re: Verilog v.s VHDL
VHDL is more verbose, but Verilog is more consice, like C language.
It is said that you can model whatever you do in VHDL in Verilog and Vice Versa.
One thing that you don't have in Verilog,however, is Record and Operator Overloading, which is rarely used in modeling the circuites, at lease when you want to synthesize the circuite.
One thing that Verilog has and VHLD lacks, on the other hand, is the fork-join block. This is a very powerful construct in Verilog that lets you have nested parallel-sequential blocks inside each other. Sometimes this feature is called multi-threading. You cannot have this in VDHL unless you use explicit synchronizations between two different processes.
Verilog is going to be even more powerful with its new generation called SystemVerilog, which has more abstract constructs equivalent to Records. Just look systemVerilog on wikipedia website.