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The comparison of Specman with OpenVera

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ldm

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Specman vs. OpenVera -> What pros & cons of each one of the tools?

Which tool is used more frequently? In which cases?

If I have a choice to learn one of them, so what choice should be better?

All comments are more than welcome.
 

Specman vs. OpenVera

Verification major in method,not the tools. The method of specman and openvera is same. openvera more easy used than specman. And just severl day before , someone tell me cadence have merge specman to a platform, may call win-manager , it's function is very powerful.
 

Re: Specman vs. OpenVera

That is ok, the method more important the tool.
Could U talk about assertion and Vear?
thanks.
 

Specman vs. OpenVera

Assertion is from software design , at software desgin , assertion can find more than 50% error, the assertion add in software lib and software , so it powerful. But at IC design , ic enginner don't like to add assertion at they code, and verification enginner just know servral place to add assertion, so assertion in ic design is limited.
 

Specman vs. OpenVera

Verification engineer often see the DUV as blackblox , so they just can add assertion at blackbox interfac. And i think the important use of assertion is used in whitebox, it can add to every where of design.
 

Specman vs. OpenVera

I suggest the specman, It is a good tool
 

Re: Specman vs. OpenVera

xworld2008 said:
Assertion is from software design , at software desgin , assertion can find more than 50% error, the assertion add in software lib and software , so it powerful. But at IC design , ic enginner don't like to add assertion at they code, and verification enginner just know servral place to add assertion, so assertion in ic design is limited.

Please take a look at John Cooley's latest survey on verification. Assertion is used in >58% of designs.
Assertions can be used in 2 distinctive verification environment -- simulation based or formal analysis based. Check out the latest C/a/d/e/n/c/e I/n/c/i/s/i/v/e tools.
 

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