buenos
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21:15 clock
hi
I would expect a toggling signal on the test pin output:
testpin <= clock; (VHDL)
but it is constant logic high, where the clock input to the FPGA is coming from an oscillator, I have measured and its OK/toggling.
hi
I would expect a toggling signal on the test pin output:
testpin <= clock; (VHDL)
but it is constant logic high, where the clock input to the FPGA is coming from an oscillator, I have measured and its OK/toggling.