testpin<=clock; not working

[buenos]

21:15 clock

hi

I would expect a toggling signal on the test pin output:
testpin <= clock; (VHDL)
but it is constant logic high, where the clock input to the FPGA is coming from an oscillator, I have measured and its OK/toggling.

 

[FvM]

edn viewref prim

Depends on where the said line is placed in the entity. If the assignment is unconditional, you're right.

 

[buenos]

it is in the middle of the logic, in between the begin of architecture and end.

why it does not put the clock to the output?

Added after 7 minutes:

oh, and it is not in a process. is it a problem?
previously with xilinx i always did this, now with Actel may it be different?

 

[shanmugaveld]

if it is inside the clock sensitivity process and change with respect to positive clock edge the o/p will always be high..

 

[buenos]

could you be more detailed? why will it be always high?

i have tried it without any processes, and ALSO within a process sensitive to clock.

Added after 1 hours 6 minutes:

if i check the EDN file, it seems it did not assign an IO buffer for these pins. why?

for another signal:
(port fpga_test2 (direction OUTPUT))
...
instance fpga_test2_pad (viewRef prim (cellRef OUTBUF (libraryRef PA3)))

for this signal:
(port fpga_test10 (direction INPUT))
i am driving it with a clock, it should NOT be an input.

 

[buenos]

shanmugaveld wrote:
"if it is inside the clock sensitivity process and change with respect to positive clock edge the o/p will always be high.. "

WHY is it so obvious?? why is it high? please provide some explanation too.

 

[vvanders]

I would guess that's because the only time the output is updated is when the clock is high(rising edge).

 

[buenos]

you mean clocking the output clock signal with itself?
this is NOT that I did.

to make it more interesting, i made few changes:
2 clock input signals (2 onboard oscillators: 66mhz, 32khz) are routed to testpin outputs without any processes. clk1 (66mhz) is clocking onchip flipflops as well, clk2 is not used on-chip. clk2 can be measured on the testpin, while clk1 output stucked high.
so sometimes it routes signals to outputs, sometimes not????? is my chip broken? actel proasic3.