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Testing an embedded core - advice needed

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swov

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Testing an embedded core

Hi,

I'm working with TetraMax to test an embedded core, the core has been IEEE1500 wrapped, and is fitted with multiple internal scan-chains.

Lets say I have bought a mp3 decoder as a Hard IP-core. And the designer has given me his design and have embedded it into my design. The designer also provided me with test-patterns to test his core.

Now it is part of my design and IEEE1500 gives me direct access to the core. The scan-chains aswell as the in and outputs of the core via the IEEE1500 Wrapper Boundary Register. So I can use the patterns the core-provider has given me, but as of yet I have found no way of telling Tetramax it should use them, or how it should be done.

Tetramax has the a pattern mapping feature for internal cores with previously generated patterns, but it is unable to perform the mapping as this mapping functionality does not support the load_unload operations in the provided test-paterns (Which I believe are vital for a core with scan chains)

does anybody of you guys know of a way to proceed?
 

swov

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Re: Testing an embedded core

Does anybody have any experience with IEEE1500?
 

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