Thanks. I am new to this. Partcularly in UVM, how to make a testbench without a design/or DUT or more precisely making a testbench before the design is there and make sure it works....so that when design is available you can just instantiate it and use the same testbench....
Any example project or resources that can help me please???
Makes little sense! Do you understand how a test-bench works?
It drives some signals, and waits for some response from the DUT, after which the TB makes a decision. So if you have no DUT, how do you expect to get a proper response?
A workaround is to use a design that is similar in functionality with the real future design, and use it to test your TB ! That being said, the temp_DUT interface must be exactly matching with the real_future_DUT.
If you are new to "all this", and you have little experience with testbenches, then I highly suggest you avoid UVM for now. It is very complicated to many seasoned designers, let alone newbies. You need to get yourself up to speed with SV before you even think of UVM.
I understand that. I meant can I have some sort of dummy dut to serve the purpose . Or we can have two UVM agents (one active and one passive) just to test connect them back to back wihout any dut.......
I understand that. I meant can I have some sort of dummy dut to serve the purpose . Or we can have two UVM agents (one active and one passive) just to test connect them back to back wihout any dut.......
I assume you have a Specification for the DUT, otherwise how can you write a testbench at all?
If you have the spec, then you'll have the interface. Just connect through whatever seems sensible through directly to the output.