kennyruffles
Newbie level 2
Hello there,
I'm trying to make a testbench in SystemC for a VHDL DUT.
My question is how can i access internal signals from VHDL using the SystemC?
Modelsim has macros like $init_signal_spy, $signal_force ....
Is there something like this macros for cadence tools? Is there other methodology to do this? I've read about nc_mirror but i don't know if i can use it with systemc, 'cause there is just references about vhdl and verilog co simulation.
Thanks and sorry about my bad english.
I'm trying to make a testbench in SystemC for a VHDL DUT.
My question is how can i access internal signals from VHDL using the SystemC?
Modelsim has macros like $init_signal_spy, $signal_force ....
Is there something like this macros for cadence tools? Is there other methodology to do this? I've read about nc_mirror but i don't know if i can use it with systemc, 'cause there is just references about vhdl and verilog co simulation.
Thanks and sorry about my bad english.
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