Here is a way to test ur FIR filter...
1. Get VHDL or Verilog code for FIR filter ready.
2. Generate data file for (sine+ noise) using C or any other scripting file.
This you can do in C simply as follows..
for (i=0; i< MAX_DATA_POINTS; i++) {
data = sine(i) + rand();
fprintf(data_file, "%.32x\n", data);
}
You can generate sine+noise in Verilog testbench directly also
you have to write ur verilog function for sine ...
data = sine(i) + $random;
3. In ur Verilog/VHDL test bench read data value from data file and
apply it to FIR filter input each clock!
Hope this helps..