testbench for VHDL - project

[kidi3]

I created a test bench where i want to test the interaction between 2 components, but for some reason does my testbench not recognize my head (topmodule). which has all my components.

Some form of clarification would help here.

Testbench: head_tb.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity head_tb is
end head_tb;

architecture Behavioral of head_tb is
COMPONENT head
Port (  
     CLK: in std_logic;
     PWM_h : out std_logic;
     debug_led: out std_logic;
     MISO : in STD_LOGIC;
     MOSI : out STD_LOGIC;
     CS : out STD_LOGIC;
     SCLK : out STD_LOGIC;
     tx_pwm: out std_logic_vector( 1 downto 0);
     rx_pwm: in std_logic_vector ( 1 downto 0)
     );
END Component;

signal CLK:         std_logic := '0';
signal PWM_h:       std_logic := '0';
signal debug_led:   std_logic := '0';
signal MISO:        std_logic := '0';
signal MOSI:        std_logic := '0';
signal CS:          std_logic_vector(5 downto 0) := "000000";
signal SCLK:        std_logic := '0';
signal tx_pwm:      std_logic_vector(1 downto 0) := "00";
signal rx_pwm:      std_logic_vector(1 downto 0) := "00";
constant period :time := 10ns;

begin

UUT: SPI port map(
      CLK => CLK,
      SCLK => SCLK,
      CS => CS,
      MISO => MISO,
      tx_pwm => tx_pwm,
      MOSI => MOSI
    );

UUT: pwm01 port map(
       CLK => CLK,
       pwm => pwm_h,
       debug_led => debug_led,
       rx_pwm => rx_pwm 
    );  
    
CLK  <= not clk after period;

ADC: process
begin
    MISO <= '1';
    wait for 50 ms; 
    MISO <= '0';
    wait for 50 ms; 
end process;

end Behavioral;

topmodule: head.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity head is
    Port ( 
        CLK: in std_logic;
        PWM_h : out std_logic;
        debug_led: out std_logic;
        MISO : in STD_LOGIC;
        MOSI : out STD_LOGIC;
        CS : out STD_LOGIC;
        SCLK : out STD_LOGIC;
        tx_pwm: out std_logic_vector( 1 downto 0);
        rx_pwm: in std_logic_vector ( 1 downto 0)
  
    );
end head;

architecture Behavioral of head is
component main 
port(
        MISO : in STD_LOGIC;
        MOSI : out STD_LOGIC;
        CS : out STD_LOGIC;
        SCLK : out STD_LOGIC;
        CLK : in STD_LOGIC;
        tx_pwm : out std_logic_vector(1 downto 0)
    );
end component;

component pwm 
port(
       CLK : in STD_LOGIC;
       PWM : out std_logic;
       debug_led: out std_logic;
       rx_pwm : in std_logic_vector (1 downto 0)
    );
    
end component;

signal buf : std_logic_vector(1 downto 0) := "00";

begin

SPI: main port map (
    CLK => CLK,
    SCLK => SCLK,
    CS => CS,
    MISO => MISO,
    tx_pwm => buf,
    MOSI => MOSI
);

pwm01:  PWM port map (
    CLK => CLK,
    pwm => pwm_h,
    debug_led => debug_led,
    rx_pwm => buf
);
end Behavioral;

I get the error messages that <spi>, <uut>, and <pwm01> is not declared when i run my test bench.

 

[K-J]

Well your testbench instances a component called 'SPI' and 'pwm01', but those entities are never defined. Similarly, 'head' calls out 'main' and 'PWM', but those entities are not defined. I think you're confusing the entity/component name with the label. You probably want to say 'UUT : head port map(...'.

Additionally, you don't need to define components, they can be troublesome if the component definition does not match the entity. To instance a widget without a component you simply say 'UUT : entity work.head port map(...'. Less error prone.

Kevin Jennings

 

[kidi3]

I not sure if I understand it correctly...
Within the test bench you would write

UUT: main SPI port map (..

or am I misunderstanding something?

 

[ads-ee]

I not sure if I understand it correctly...
Within the test bench you would write

UUT: main SPI port map (..

or am I misunderstanding something?

Yeah you are misunderstanding something....

UUT : entity work.head port map(...

This instantiates the entity using direct instantiation (i.e. without a component declaration).