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[SOLVED] testbench for generic mux

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M

meliT

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Hi guys,
Can any one help me with the error for the below generic code for mux, please:
Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.numeric_std.all;
--------------------------
--------------------------
package type_def_pack is
  
  constant s: integer := 5;
  constant line_width: integer := 1;
  type wire is array (0 downto 2**s -1) of std_logic_vector(line_width-1 downto 0);
  
end package;  
  
--------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.numeric_std.all;

library work;
use work.type_def_pack.all;
--------------------------
entity Generic_Mux is 
 
--  generic ( line_width : integer := 1);
  port ( Dinput : in wire;
         sel : in std_logic_vector (s-1 downto 0);
         output : out std_logic_vector(line_width-1 downto 0));
end Generic_Mux;
-------------------------
architecture behavioral of Generic_Mux is
BEGIN
	output <= Dinput(conv_integer(sel));
END architecture behavioral;
-------------------------
-------------------------

library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

library work;
use work.type_def_pack.all;
-------------------------
-------------------------
entity TB_GenMux is 
--  generic ( line_width : integer := 1);
end TB_GenMux;
-------------------------
architecture behavioral of TB_GenMux is

signal TDinput : wire;
signal Tsel: std_logic_vector (s-1 downto 0);
signal Toutput: std_logic_vector(line_width-1 downto 0);

component Generic_Mux is 
--  generic ( line_width : integer := 1);
  port ( Dinput : in wire;
         sel : in std_logic_vector (s-1 downto 0);
         output : out std_logic_vector(line_width-1 downto 0));
end component;

begin
  UUT: Generic_Mux
 -- generic map( line_width => line_width )
  port map ( Dinput => TDinput, sel => Tsel, output => Toutput);
  
  P:process
  begin
    TDinput (line_width*1-1 downto line_width*0)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*2-1 downto line_width*1)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*3-1 downto line_width*2)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*4-1 downto line_width*3)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*5-1 downto line_width*4)<= std_logic_vector (to_signed (0,line_width));    
    TDinput (line_width*6-1 downto line_width*5)<= std_logic_vector (to_signed (0,line_width));  
    TDinput (line_width*7-1 downto line_width*6)<= std_logic_vector (to_signed (1,line_width));    
    TDinput (line_width*8-1 downto line_width*7)<= std_logic_vector (to_signed (0,line_width));        

    TDinput (line_width*9-1 downto line_width*8)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*10-1 downto line_width*9)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*11-1 downto line_width*10)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*12-1 downto line_width*11)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*13-1 downto line_width*12)<= std_logic_vector (to_signed (1,line_width));    
    TDinput (line_width*14-1 downto line_width*13)<= std_logic_vector (to_signed (1,line_width));  
    TDinput (line_width*15-1 downto line_width*14)<= std_logic_vector (to_signed (1,line_width));    
    TDinput (line_width*16-1 downto line_width*15)<= std_logic_vector (to_signed (0,line_width));        

    TDinput (line_width*17-1 downto line_width*16)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*18-1 downto line_width*17)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*19-1 downto line_width*18)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*20-1 downto line_width*19)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*21-1 downto line_width*20)<= std_logic_vector (to_signed (1,line_width));    
    TDinput (line_width*22-1 downto line_width*21)<= std_logic_vector (to_signed (0,line_width));  
    TDinput (line_width*23-1 downto line_width*22)<= std_logic_vector (to_signed (0,line_width));    
    TDinput (line_width*24-1 downto line_width*23)<= std_logic_vector (to_signed (1,line_width));        

    TDinput (line_width*25-1 downto line_width*24)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*26-1 downto line_width*25)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*27-1 downto line_width*26)<= std_logic_vector (to_signed (1,line_width));
    TDinput (line_width*28-1 downto line_width*27)<= std_logic_vector (to_signed (0,line_width));
    TDinput (line_width*29-1 downto line_width*28)<= std_logic_vector (to_signed (1,line_width));    
    TDinput (line_width*30-1 downto line_width*29)<= std_logic_vector (to_signed (1,line_width));  
    TDinput (line_width*31-1 downto line_width*30)<= std_logic_vector (to_signed (0,line_width));    
    TDinput (line_width*32-1 downto line_width*31)<= std_logic_vector (to_signed (1,line_width));        

    Tsel <= "00000"; wait for 10 ns;    
    Tsel <= "00001"; wait for 10 ns;        
    Tsel <= "00010"; wait for 10 ns;    
    Tsel <= "00011"; wait for 10 ns;        
    Tsel <= "00100"; wait for 10 ns;    
    Tsel <= "00101"; wait for 10 ns;    
    Tsel <= "00110"; wait for 10 ns;    
    Tsel <= "00111"; wait for 10 ns;    
    
    Tsel <= "01000"; wait for 10 ns;    
    Tsel <= "01001"; wait for 10 ns;        
    Tsel <= "01010"; wait for 10 ns;    
    Tsel <= "01011"; wait for 10 ns;        
    Tsel <= "01100"; wait for 10 ns;    
    Tsel <= "01101"; wait for 10 ns;    
    Tsel <= "01110"; wait for 10 ns;    
    Tsel <= "01111"; wait for 10 ns;    
    
    Tsel <= "10000"; wait for 10 ns;    
    Tsel <= "10001"; wait for 10 ns;        
    Tsel <= "10010"; wait for 10 ns;    
    Tsel <= "10011"; wait for 10 ns;        
    Tsel <= "10100"; wait for 10 ns;    
    Tsel <= "10101"; wait for 10 ns;    
    Tsel <= "10110"; wait for 10 ns;    
    Tsel <= "10111"; wait for 10 ns;    
    
    Tsel <= "11000"; wait for 10 ns;    
    Tsel <= "11001"; wait for 10 ns;        
    Tsel <= "11010"; wait for 10 ns;    
    Tsel <= "11011"; wait for 10 ns;        
    Tsel <= "11100"; wait for 10 ns;    
    Tsel <= "11101"; wait for 10 ns;    
    Tsel <= "11110"; wait for 10 ns;    
    Tsel <= "11111"; wait for 10 ns;    
    
    
  end process;
end architecture behavioral;

the error is in line 37 and says:
** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/final/TB/TB_GenMux.vhd(37): (vcom-1146) No value can belong to null range 0 downto 31.
** Error: C:/Users/Melika/Desktop/Advanced VLSI/Assignment 4/final/TB/TB_GenMux.vhd(37): (vcom-1154) No index value can belong to null index range 0 downto 31.

Thanks
 

Dinput is declared as a wire and not as a vector. So "Dinput(conv_integer(sel))" is not valid.
 

Sure it is a wre type, the point is that the line :
Code: 
 type wire is array (0 downto 2**s -1) of std_logic_vector(line_width-1 downto 0);
has synthax error : downto ---> to
but if even this error is coverd, assigning the values to TDinput has error, and the error says:
Target type work.type_def_pack.wire in signal assignment is different from expression type ieee.std_logic_1164.std_logic_vector.
I don't know what can I do with it, 'caz I have no chance to change the type of Dinput.
Please help if u have any idea.
Thanks
 

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