If Setup and Hold times exceed designed wait times, errors can occur.
But this is only one of a dozen or more mechanisms that can influence SNR and BER.
Many different algorithms to determine optimal settings or reliability have different tradeoffs for test time vs fault coverage.
Adjacent cell, pattern dependent at full speed is one of many tests.
Just as in CPU SRAM delay controls, BIOS uses an algorithm to provide a quick sample test of various patterns.
Memtest86+ has a dozen or so different patterns.for example on PC's, you may check.