module tb_thresolding(
);
//**************** input declarations**********************//
reg clk; // input pixel clock
reg n_rst; // active low reset
reg sof; // single pulse to indicate valid sigma
reg [23:0]sigma; // sigma data
reg [7:0] diff_in; // read data from memory
reg diff_val;
//*************** output declarations*********************//
wire mask_mem_wr_en; // memory write enable
wire [18:0]mask_mem_wr_addr; // memory write address
wire mask_mem_wr_data; // memory write data
wire eoth; // end of thresolding
wire mask_packmem_wr_en; // write enable for packed data
wire [18:0]mask_packmem_wr_addr; // write address for packed data
wire [15:0]mask_packmem_wr_data ; // pack 16 bits of output data
reg Mask_mem [414719:0];
reg mask_mem_mat_data;
//DUT
thresolding THR(
.clk (clk ),
.n_rst (n_rst ),
.sof (sof ),
.sigma (sigma ),
.diff_in (diff_in ),
.diff_val (diff_val ),
.mask_mem_wr_en (mask_mem_wr_en ),
.mask_mem_wr_addr (mask_mem_wr_addr ),
.mask_mem_wr_data (mask_mem_wr_data ),
.mask_packmem_wr_en (mask_packmem_wr_en ),
.mask_packmem_wr_addr (mask_packmem_wr_addr ),
.mask_packmem_wr_data (mask_packmem_wr_data ),
.eoth (eoth )
);
integer i;
reg [7:0]temp;
integer fp1,fp2,fp3,fp4,fp5;
reg [20:0]count;
initial
begin
clk = 0;
n_rst = 0;
sof = 0;
diff_in = 0;
diff_val = 0;
//10
//sigma = 81557;
//11
//sigma = 82130;
//12
//sigma = 82873;
//13
//sigma = 83473;
//14
//sigma = 84390;
//15
//sigma = 85146;
//16
//sigma = 85316;
//17
//sigma = 85455;
//18
//sigma = 86072;
//19
//sigma = 86263;
//20
//sigma = 87047;
//21
// sigma = 87340;
//22
//sigma = 87783;
//23
//sigma = 88689;
//24
//sigma = 89367;
//25
sigma = 89499;
i = 0;
mask_mem_mat_data=0;
count = 0;
fp1 = $fopen("inputframe.txt","r");
fp2 = $fopen("Matlab_output.txt","r");
fp3 = $fopen("RTL_output.txt","w");
repeat(5)
@ (posedge clk);
n_rst = 1;
@ (posedge clk);
sof = 1;
@(posedge clk);
sof = 0;
while(!$feof(fp1))
begin
@ (negedge clk);
fp4= $fscanf(fp1,"%d\n",diff_in);
diff_val <=1;
end
@(negedge clk);
diff_val <= 0;
end
always #10 clk = !clk;
// memory model
always @(posedge clk)
begin
if(mask_mem_wr_en)
Mask_mem[mask_mem_wr_addr] <= mask_mem_wr_data;
end
// comparision logic
always @(negedge clk)
begin
if(mask_mem_wr_en)
begin
$fwrite(fp3," %d\n",mask_mem_wr_data);
fp5 = $fscanf(fp2,"%d\n",mask_mem_mat_data);
if(mask_mem_mat_data ==mask_mem_wr_data)
begin
$display("%0dns Match : input and output match",$time);
$display(" Got %h",mask_mem_wr_data);
$display(" Exp %h",mask_mem_mat_data);
count <=count;
end
else
begin
count <= count + 1;
$display("%0dns Error : input and output does not match",$time);
$display(" Got %h",mask_mem_wr_data);
$display(" Exp %h",mask_mem_mat_data);
end
end
end
always @(posedge clk)
begin
if(eoth)
begin
if(count ==0)
begin
$display("RTL Output and matlab outputs are matched \n number of errors are :%d",count);
end
else
begin
$display("RTL Output and matlab outputs are not matched \n number of errors are:%d",count);
end
end
end
endmodule