Test and dft logic verification in flow and the lec

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fragnen

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During lec we deactivate the test related logic and dft related logic by providing suitable constraints? When in the flow are these test and dft related logics are verified for the synthesized netlist?
 

These test and dft related logics are verified during ATPG (for example, by Synopsys TetraMax tool). Also, some kind of verification exist in Synopsys DFTcompiler (as a part of DesignCompiler).
 

Is not it better to verify the test related cones also during LEC by not deactivating the test related logic and dft related logic by providing suitable constraints?

Regards
 

DFT related logic (scan chain, scan_enable connection... are inserting during synthesis. It does not exist in RTL. So, LEC gate vs RTL will fail.
 

oratie said:
DFT related logic (scan chain, scan_enable connection... are inserting during synthesis. It does not exist in RTL. So, LEC gate vs RTL will fail.
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What are the other DFT related logic other than scan chain, scan_enable connection that are inserted during synthesis and not present in rtl?
 

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