I see two uses for Generics in a VHDL entity:
1. To provide a Name to an otherwise magic number, but where the value is never intended to be changed.
2. A Parameter that allows the entity function to be changed from instance to instance.
Eg:
Code VHDL - [expand] |
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| entity Multiply16Bit is
generic
(
WIDTH : integer := 16
);
port
(
clk_in : in std_logic;
a_in : in std_logic_vector ( (WIDTH - 1) downto 0) := (others => '0');
b_in : in std_logic_vector ( (WIDTH - 1) downto 0) := (others => '0');
mult_out : out std_logic_vector ( (WIDTH - 1) downto 0) := (others => '0')
);
end Multiply16Bit; |
Here the entity is a 16 bit multiplier. WIDTH is intended to be used to define the width of the interface, but it is not intended to be changed. It is a 'fixed value'. Allowing it to change may make implementation difficult, or would require testing at different widths or whatever.
'WIDTH' is just used to put a Name to what would otherwise be '16' (a potentially meaningless value).
and:
Code VHDL - [expand] |
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| entity Delay_1 is
generic (
--! Data width parameter
DATA_WIDTH : integer := 16
);
port
(
--! Clock input
clk_in : in std_logic;
--! Data Input
data_in : in std_logic_vector((DATA_WIDTH - 1) downto 0);
--! Data Output
data_out : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
end Delay_1; |
Here the intention is that DATA_WIDTH can be changed to any values as required for each instance. It is a 'parameter'.
What I am trying to determine is how to enforce or encourage users to make a distinction between these two uses, and ensure that 'fixed value' generics don't get changed. Maybe there is a convention of a name prefix or suffix that can indicate one or other. Of course comments can indicate the usage. An ASSERT would also be another way to ensure a fixed value does not get changed.
Any ideas? Are there any standard conventions for such things?
Clayton
Canberra, Australia