[SOLVED] task in blocking statements

[rocking_vlsi]

Hi

Please read the code below and

//////////////////////////////////////////////////////////
reg gbl_reg ;
reg temp1;

task simple_task
input a;
begin
gbl_reg=a;
end
endtask


always@(*)
temp1=0;
simple_task(0);

case(fsm_state)
state1: begin
temp1=1;
simple_task(1);
end
state2: begin
temp1=0;
simple_task(0);
end
endcase

//////////////////////////////////////////////////////////

I am unable to understand which value will be assigned to temp1 and gbl_reg ?
Everytime the fsm_state changes, will temp1 and gbl_reg are assigned value 0. and depending on the fsm_state, temp1 and gbl_reg are assigned later.

 

[dave_59]

You can make multiple assignments to the same variable in the same always process, and the last write 'wins'. People code this way when they have a lot of variables, and the case statement branches only have assignments to variables that are different from the default.

 

[rocking_vlsi]

Thanks Dave. One of my other concern is task invocation. Does only one task get invoked based on the condition?

Because I am assigning a value to global register inside the task and if earlier task does not complete before the next task invocation then value may get over written. Please correct me if i am wrong?

 

[dave_59]

It doesn't matter. In your case, that task has no blocking statements; it could have been written as a function. Even if it did have blocking statements, you could (and should) declare the task as automatic so that the value of a does not get overwritten by another concurrent task.

If you can use SystemVerilog, you should declare any task as a function that does not block as a function void. That is a guarantee that it will never block.