Target slack unconstrained after synthesis

[kannanunni]

What is the reason for showing "Target slack unconstrained" after synthesis???
and there also shows no generated clock found for "report clocks -generated" command in RC?

rc:/> report clocks -generated
================================================== ==========
Generated by: Encounter(R) RTL Compiler v09.10-p104_1
Generated on: Jan 25 2011 12:01:28 PM
Module: soc_top
Technology library: NangateOpenCellLibrary revision 1.0
Operating conditions: typical (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
================================================== ==========

No clocks to report


but i given a clock constraint like this..

rc:/> report clocks
================================================== ==========
Generated by: Encounter(R) RTL Compiler v09.10-p104_1
Generated on: Jan 25 2011 12:02:19 PM
Module: soc_top
Technology library: NangateOpenCellLibrary revision 1.0
Operating conditions: typical (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
================================================== ==========


Clock Description
-----------------

Clock Clock Source No of
Name Period Rise Fall Domain Pin/Port Registers
---------------------------------------------------------------
clk 10000.0 0.0 5000.0 domain_1 0

Clock Network Latency / Setup Uncertainty
-----------------------------------------

Network Network Source Source Setup Setup
Clock Latency Latency Latency Latency Uncertainity Uncertainity
Name Rise Fall Rise Fall Rise Fall
------------------------------------------------------------------------
clk 0.0 0.0 0.0 0.0 0.0 0.0

Clock Relationship (with uncertainity & latency)
-----------------------------------------------

From To R->R R->F F->R F->F
---------------------------------------------------
clk clk 10000.0 5000.0 5000.0 10000.0



Please do reply..

 

[englishdogg]

report_clocks -generated is empty cause you have no generated clocks defined.. have you?
You have a clock named "clk" defined which reflects; target slack unconstrained is may be cause your not reporting the correct endpoints or there is no timing path for the path you wish to report.

 

[kannanunni]

report_clocks -generated is empty cause you have no generated clocks defined.. have you?
You have a clock named "clk" defined which reflects; target slack unconstrained is may be cause your not reporting the correct endpoints or there is no timing path for the path you wish to report.

how should i define generated clock?

and actually this target slack unconstrained shows in the initial optimization phase. so what's the reason?

 

[englishdogg]

pls go through the SDC reference once anyways the command is :create_generated_clock
I am not sure when you say initial phase of optimization .. pls push the snippet of the log

 

[kannanunni]

ok that's solved..
now i have another problem..

Error : Unable to map design without a tristate buffer or inverter. [MAP-1] [synthesize]
: The design is 'minsoc_top'.
: Check the libraries for necessary tristate cell. The cell could be marked unusable.

so
how to find tristate inverter from timing lib???

 

[englishdogg]

It says that the lib is marked unusable i.e. set_dont_use

Basically all tri-state inverter libcells are marked false so it should be easy to find in the lib.

Try playing with the "find" command