Tapeout Issues - Nearing Deadline.

[g.s.javed]

HI,

Happy New Year 2012 to all.

I have a few issues in layout. The Technology we are using is UMC 130nm 1P8M CMOS process. I am designing a oversampled ADC.
I have a tape out coming up ( 15 Jan '12 ).

1. I have to bring DC signals from outside the chip to be used as a reference signal. There are about 4 signals. Each of them have to be buffered before they can be brought in and used.
Which configuration is the best for buffering these signals ? .

2. All these signals(reference voltage signals) need to have ESD protection circuit to prevent charge injection and allied effects. Generally, how do we place a ESD circuit and what configuration is used for it.

3. I have a high frequency clock coming too. The output is also a high frequency signal. BY high frequency , i mean, 6.4 MHz.
How will the buffer differ here? I am using an inverter based buffer. I am using an 5 stage inverter based buffer with a multiplication factor of 2. is this right.?

4. All the DC lines have to be Buffered. That I am aware. Any other precautions that need to followed.

5. The input also needs to be buffered too. This is audio signal. What design or configuration of buffer to be used for this.

This is my FIRST INDEPENDENT TAPEOUT. Before, there was someone else integrating the entire chip for us. Now, I have to do it. Kindly help out.

Thank you.

Javed

P.S. Give me other links(posts, threads, etc, ) here where I can get more information.

 

[Old Nick]

1 - I'm not really sure I can answer this with the information given
2 - I'm not sure for your foundry, but the processes we use have a choice of pads with varying levels of ESD protection, we would just choose the appropriate pad for whatever the signal was.
3 - If your buffer simulates driving the expected loads it should be fine.
4 - It's best to do a post layout sim to make sure you don't have large IR drops etc. and that your tracks can handle the expected currents. I have no idea what your circuit is so I can't really comment with any accuracy.
5 - whatever design meets your spec

I probably haven't been much help, but have a spec for buffers etc. design something you think will meet it, then check with sims and revise your design until it does.

 

[Braski]

pay attention to the UMC pad sometimes they are tricky. in an old release of UMC 180 nm you had to add vias by hand, they didn't add it. -.-
Hope they have fixed it with updated DKs.

 

[g.s.javed]

@Braski:

Thank you for the hint. We will try to be cautious.