Tanner EDA : DRC Check

[raghavathej]

Hi everyone,

I am using Tanner EDA Tools.

I have constructed a simple inverter in L-EDIT, while checking
for DRC Errors, there are hundreds of errors, this is because i draw everything
from scratch (much below transistor level, as we dont have PMOS and NMOS layout
symbols to use directly, i start by building the same from source, drain, gate etc).
I have also used Mentors pyxis layout editor & cadence Virtuoso layout editor. The DRC errors
over there are very easy to fix because i directly use PMOS and NMOS Transistor layouts directly.

My questions are :-
1. Will i get PMOS and NMOS layouts directly in Tanner EDA Tools as Well (I am using v16.0) ? if so please share the procedure...
2. Do i have autoroute option in Tanner EDA like Mentors Pyxis/ Cadence Virtuoso ? if so share the same..
3. Why hasn't Tanner EDA been as popular as Mentor/Synopsis/Cadence Tools considering that Tanner can also generate GDSII file.

Awaiting for you reply, Thanks in advance !!!

 

[Devesh Joshi]

Hi Raghav,

I'm also new to the L-Edit, in fact I connected morbn20.tdb file to it, but when I'm dragging Active, Poly or any other. it's not getting drawn, can you help me regarding this.

Thanks in Advance
Devesh

 

[raghavathej]

Can you share the screenshot of the same. Have you able to load layer pallete ?

 

[kodar]

So far as I know:

1. you need a PDK (process design kit) from a foundry. You have to sign a NDA to get the library. Otherwise, if you want to test and experience layout in L-Edit I suggest you to download FreePDK (https://www.eda.ncsu.edu/wiki/FreePDK). This is a PDK for education purpose. Once downloaded import the general GDS file in L-Edit. You'll get your cells. Finally you have to use rules from Calibre DRC. Have a look here https://www.eda.ncsu.edu/wiki/FreePDK45:DRC
2. Yes, this is the SPR feature.
3. Tanner EDA is popular for MEMS chips.

I hope this helps.