systolic Vs General Array

[matthew_wang]

What is the advantage of the systolic array compared with general PE array?

Could someone do me a favor to recommend some classic materials about systolic design?

Thanks

 

[eltonjohn]

The problem in systolic array is the GRID topology ..Depending on the problem is different .So to create a general purpose systolic machine is HARD
General Array is much more CONFIGURABLE .

 

[matthew_wang]

how about the cost of two kinds of design?

 

[eltonjohn]

systolic array research has been around for a while .I was interested in doing some work with reconfigurable computing using FPGA ..so the shape of the array will change according to the need of the algorithm

I have a GREAT BOOK on systolic array ..IS old like 14 years old ..BUt still very up to date /Unfortunatly in one of the few that is not in electronic form.I have thought to scan it .One day

I will post the reference later ..Is in my old library ,,be patient

 

[aslijia]

it is a trade off between the area and speed. so it is between the two kinds of array. systolic is faster but bigger, while general array is smaller but slower.

 

[matthew_wang]

I think this classic book for vector arrray processor has been updated,



but the pointes needed are too much for me, I am poor.

fast or slow, is not only point, for systolic , it is more regular and esay for backend, but others maybe cost more than systolic. The speed of other array can be slow or faster than systolic, it is not fixed.

I want to make clear that how to do trade-off between this two structure?

 

[aslijia]

it is depend on your design. you need faster or smaller, then you can choose one.

 

[matthew_wang]

I think systolic does not only mean faster and bigger, the PE array structure also can be done very fast.

 

[eltonjohn]

systolic doesn't mean bigguer ..The size is dictated by the algorithm ,and by the amount of precessing required!
systoloc and computing array are PARALLEL PIPELINES .. It mean parellism in two dimentions .: IN SPACE and in TIME .!!!
now systolic have more than 4 space dimentions computing array are only 4
north ,south,east,west .both architectures consume a lot of resources if implemented with FPGAS.because by definition :THEY don't use a routing FABRIC.but rather all logic tiles comunicate with their neighbor