Sure.
I have modules : encoder, decoder, error (this flips random bits of data and sends it to the encoder which then sends it to the decoder which corrects the data).
I havent used any clock. I have a testbench which sends the data to the error module as well as parity module (as this parity is used along with my input data; and this entire data is used to flip a single bit in error module).
i have a for loop in error module which lets me add errors at different locations and check if my decoder does its job.
Now, when I send a second data (with a delay), all these module use the last data to do their job. And the first data only displays ( i have display statements in my testbench)